Digital data conversion equipment and a method for the same

ABSTRACT

In digital data conversion apparatus and method, class data are generated in association with reference interpolated data for each of a plurality of classes on the basis of a reference high definition digital video signal which includes a reference standard definition digital video signal in addition to the reference interpolated data. The class data is stored at respective addresses in a memory. A standard definition digital video signal representing pixel values is received and then clustered so as to produce a class corresponding to the pixel values of the standard definition digital video signal. The class data is retrieved from the memory address which corresponds to the class of the standard definition digital video signal, and interpolated data is generated in accordance with the standard definition digital video signal and the retrieved class data with such interpolated data constituting a high definition digital video signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a digital data conversion equipment and amethod for the same, which are applicable to an interpolation of athinned picture element in data conversion, up-conversion for convertinga television signal with standard resolution into a television signalwith high resolution and so on.

2. Description of the Prior Art

There are generally two kinds of systems for converting a digital videosignal. One of them is a system for converting a signal whose resolutionis high with respect to the space or time or a signal having a largeamount of information into a signal of a low resolution. The other is asystem for converting, on the contrary, a signal whose resolution is lowwith regard to the space or time or a signal having a small amount ofinformation signal of a high resolution.

In the former case, a signal having inherently a large informationamount is converted into a signal of a small information amount. Forexample, by properly thinning out a picture element information amountor field/frame information, a signal of a low space/time resolution canbe easily formed.

The above example relates to what is called a down converter to, forinstance, convert a video signal of a high definition (HD) system into avideo signal of a standard definition (SD) system. Various kinds oftechniques have already been proposed.

The latter case relates to up conversion to, for example, convert avideo signal of the SD system to a video signal of the HD system. Anexample in which an electronic zooming process is executed or anenlargement of an image is performed is considered. In those examples,hitherto, information which inherently lacks is interpolated by using aninterpolation filter and the interpolated information is used.

As still another example, there is a sub-sampling method forperiodically thinning out pixel data in order to compress arecording/transmission data amount in the case where a capacity of therecording/transmitting system is limited. In this case, the imagesthinned out are interpolated on the reproducing/receiving side by usingan interpolation filter.

However, there is a problem that the resolution of an output pictureobtained by interpolation with a filter is degraded. For example, evenif a HD television signal is formed by interpolating a SD video signalby a filter, an HD component (high frequency component) which is notpresent in an input SD signal is not reproduced. As a result, thespatial resolution of an output picture is lowered.

OBJECTS AND SUMMARY OF THE INVENTION

An object of the invention is to provide digital data conversionequipment and a method for the same capable of reproducing a highresolution component.

According to an aspect of the present invention, there is provided adigital data conversion equipment, comprising:

-   -   means for analyzing plural input data and performing clustering        depending on a distribution state of the plural input data;    -   means for generating class data associated with output data for        each class on the basis of the plural input data and known        output data;    -   memory means for storing the class data at an address        corresponding to the class;    -   read-out means for reading out class data at an address        corresponding to class information subjected to clustering based        on the plural input data; and    -   output data generating means for generating output data based on        output class data of the read-out means.

According to another aspect of the present invention, there is provideda digital data conversion method, comprising:

-   -   training step for analyzing plural input data, performing        clustering depending on a distribution state of the plural input        data, generating class data associated with known output data        for every class on the basis of the plural input data and the        output data, and storing the class data into a memory depending        on the class;    -   step for clustering the plural input data and reading out class        data at an address of the memory corresponding to the class; and    -   step for generating output data based on the class data.

The above, and other, objects, features and advantage of the presentinvention will become readily apparent from the following detaileddescription thereof which is to be read in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a transmission system to whichthe invention is applied;

FIG. 2 is a schematic diagram showing a position relation of pictureelements;

FIG. 3 is a block diagram of one example of a structure for generating amapping table;

FIG. 4 is a block diagram of another example of a structure forgenerating a mapping table;

FIG. 5 is a block diagram of another embodiment;

FIG. 6 is a schematic diagram showing a position relation of pictureelements of a SD picture and a HD picture; and

FIG. 7 is a block diagram of one example of a structure for generating amapping table.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereunder, one embodiment of this invention will be explained. This oneembodiment transmits thinned and compressed data and reproduces athinned picture element on the reception side. FIG. 1 shows such atransmission system as a whole. In FIG. 1, reference numeral 1 is aninput terminal for digital video data to be transmitted.

Input digital video data is supplied to a sampling circuit 2, andpicture element data positioned alternately is thinned out in thehorizontal direction. As shown in FIG. 2, picture elements indicated atX in the array of the original picture elements show the thinned pictureelements a result, with this thinning-out process, the data amountnecessary for transmission is reduced to half.

The output data of the sampling circuit 2 is supplied to an encoder forhighly efficient coding. For the highly efficient coding, orthogonalconversion coding such as DCT (Discrete Cosine Transform), ADRC (DynamicRange Adaptive-type Coding) and so on, which are well known, can beadopted. With this encoder 3, the data amount to be transmitted isreduced.

The output data of the encoder 3 is fed to a transmission processingcircuit 4. The transmission processing circuit 4 performs processingsuch as error correction coding, frame formation and channel coding.Transmission data is generated at an output terminal 5 of thetransmission processing circuit 4. The transmission data is suppliedthrough a transmission line 6. The transmission line 6 is limited to acommunication line and includes processes of magnetic recording andreproduction in its meaning.

Reception data is fed through an input terminal 7 to a receptionprocessing circuit 8. The reception processing circuit 8 performsprocessing such as decoding of channel coding, frame decomposition, anderror correction. The output of the reception processing circuit 8 issupplied to a decoder 9 for highly efficient coding. The decoded outputof the decoder 9 is supplied to a selecting circuit 10 and asimultaneous output circuit 11.

The simultaneous output circuit 11, as shown in FIG. 2, producestransmission picture element data a, b, c, and d, which are present atupper and lower positions and left and right positions with respect to athinned picture element x to be interpolated, to a clustering circuit 12and an interpolation data generating circuit 14, simultaneously. Outputdata from the clustering circuit 14, i.e., class information, is givento a memory 13 as an address signal.

A mapping table for data conversion formed in a manner mentioned lateris stored in the memory 13. In this example, a mapping table includingplural parameters is stored in the memory 13. A parameter read out froman address corresponding to the output data of the clustering circuit 12is supplied to the interpolation data generating circuit. Theinterpolation data generating circuit 14 provides interpolation data xby the calculation of:

x=w1a+w2b+w3c+w4d

using transmission picture element data a, b, c, and d from thesimultaneous output circuit 11 and parameters w1, w2, w3, and w4 fromthe memory 14.

The interpolated data x is supplied to the selecting circuit 10. Theselecting circuit 10 selects the output of the decoder 9 when atransmission picture element is present, while the selecting circuit 10selects interpolated data from the interpolation data generating circuit14 at a position of a thinned picture element. Consequently, decodedvideo data corresponding to reception data is provided at an outputterminal 15 of the selecting circuit 10.

A mapping table formed in advance by training is stored in the memory13. FIG. 3 shows a structure for forming the mapping table. In FIG. 3, adigital video signal is supplied to terminal 21 and to a simultaneousoutput circuit 22. It is desirable that the digital video signal is astandard signal taking into account the generation of a mapping table.For example, for the video signal, a signal composed of a still picturewith various patterns can be adopted. As shown in FIG. 2, thesimultaneous output circuit 22 supplies a data memory 23 and aclustering circuit 24 simultaneously with a data x, which is a targetpicture element, and picture element data a, b, c, and d, which arepresent in upper and lower positions and left and right portions withrespect to the data x. It is to be noted that an actual value existswithout any thinning of the target picture element at the time of thetraining shown in FIG. 3.

The clustering circuit 24 carries out the clustering picture elementdata to generate class information as the clustering circuit 12 of FIG.1 does. For clustering, clustering by gradation, clustering by apattern, etc., can be used. In the use of the gradation, the number ofclasses becomes extremely large if picture element data has eight bits.As a result, it is desirable that the bit number of each picture elementis reduced with highly efficiency coding such as ADRC. For pattern use,plural patterns composed of four picture elements (for example,evenness, increase of a value in the right and upper direction, decreaseof a value in the right and lower direction, etc.) are prepared, and theoutput data of the simultaneous output circuit 22 is classified into anyone of the plural patterns.

The output of the clustering circuit 24 is given to one input terminal25a of a switching circuit 25. The output of a counter 26 is supplied tothe other input terminal 25b of the switching circuit 25. The counter 26generates addresses, which sequentially change, by counting clock CK.The output of the switching circuit 25 is supplied to the data memory 23and a memory 28 for parameters as their addresses.

Sample values of picture element a, b, c, d, and x are written into thedata memory 23 with respect to addresses which are class information.For example, (a₁₀, a₂₀, . . . , a_(n0)) with respect to the pictureelement data a, (b₁₀, b₂₀, . . . , b_(n0)) as to the picture elementdata b, (c₁₀, c₂₀, . . . , c_(n0)) with respect to the picture elementdata c, and (d₁₀, d₂₀, . . . , d_(n0)) as to the picture element data dare stored in a certain address AD0 of the data memory 23. As for otheraddresses from the clustering circuit 24, picture element data is storedin the memory 23 similarly.

Next, the switching circuit 25 is switched from the input terminal 25ato 25b, and the content of the data memory 23 is sequentially read outby an address from the counter 26. The read-out of the data memory 23 issupplied to an arithmetic circuit 27 of the least square method. Withthis minimum square method, parameters w1 to w4 are obtained withminimum error.

When attention is paid to one address, the following simultaneousequations are established with respect to this address:x1=w1a1+w2b1+w3c1+w4d1x2=w1a2+w2b2+w3c2+w4d2...xn=w1an+w2bn+w3cn+w4dn

Now, since x1 to xn, a1 to an, b1 to bn, c1 to cn, and d1 to dn areknown in advance, the parameters w1 to w4 are obtained so that thesquare of the error for x1 to xn (actual values) is minimized. Thisapplies to other addresses.

The parameters w1 to w4 obtained at the arithmetic circuit 27 arewritten into a memory 28. A mapping table which has been written intothe memory 28 is stored in the memory 13 of FIG. 1. Therefore, the valueof x, which is a thinned picture element, is produced at theinterpolation data generating circuit 14 using the parameters producedfrom the memory 13.

For the mapping table, not only the above-stated parameters but also theone from which output data values themselves are provided may beemployed. In this case, the interpolation data generating circuit 14 inFIG. 1 can be omitted. FIG. 4 shows a structure for forming the mappingtable. Similarly to the structure of FIG. 3, plural picture element datamade simultaneously is supplied to the clustering circuit whose outputis supplied to a data memory 30 and a frequency memory 31 as an address.

The read-out output of the frequency memory 31 is supplied to an adder32 and added by +1. The output of the adder 32 is written into the sameaddress of the memory 31. For the memories 30 and 31, each content oftheir addresses is cleared at zero as the initial stage.

Data read from the data memory 30 is supplied to a multiplier 33 andmultiplied by a frequency which is read out of the frequency memory 31.The output of the multiplier 33 is given to an adder 34 and added to theinput data x there. The output of the adder 34 is supplied to a divider35 as a dividend. To the divider 35, the output of the adder 32 is fedas a divisor. The output of the divider 35 (quotient) becomes input dataof the data memory 30.

In the above-mentioned structure of FIG. 4, data x1 is directly writteninto the memory 30 and the value of a corresponding address of thememory 31 is brought to 1, since the read outputs of the memories 30 and31 are zero. If this address is accessed once again later, the output ofthe adder 32 is 2, and the output of the adder 34 is (x1+x2). As aresult, the output of the divider 35 is (x1+x2)/2, which is written intothe memory 30. On the other hand, the frequency z is written into thefrequency memory 31. Further, when the above-mentioned address isaccessed, the data of the memory 30 is updated to (x1+x2+x3)/3. Thefrequency is also updated to 3.

By carrying out the above-mentioned operation within a determinedperiod, a mapping table is stored into the memory 30 so that data, whichis present at that time, is output when a class is designated by theoutput of the clustering circuit. In other words, when plural pictureelement data of an input video signal is given, a mapping table can beformed so that data is output to correspond to its clustered data on theaverage.

Another embodiment of the invention shown in FIG. 5 is for up-conversionof a SD video signal to a HD video signal. In FIG. 5, a digital SD videosignal is supplied to a terminal indicated at 41. Examples of the SDvideo signal are a reproduction signal, a broadcast signal, etc., ofSDVTR. The SD video signal is given to a simultaneous output circuit 42whose output data is supplied to clustering circuit 43. The output ofthe clustering circuit 43 is Sent as an address signal to memories 44ato 44d where mapping tables M1 to M4 are stored.

FIG. 6 partially shows a relationship between a SD picture and a HDpicture. In FIG. 6, picture element data interpolated by circles Obelongs to the SD picture, while picture element data indicated bycrosses X belongs to the HD picture. For example, four picture elementdata y1 to y4 of the HD picture is generated from twelve picture elementdata of the SD picture. The mapping table M1 of the memory 44a is forgenerating picture element data y1, while the mapping tables M2, M3, andM4 are for generating picture element data y2, y3, and y4, respectively.

The read-out outputs of the memories 44a to 44d are given to a selector45. The selector 45 is controlled by the output of a selection signalgenerating circuit 46. A sampling clock of the HD picture is suppliedfrom an input terminal 47 to the selection signal generating circuit 46.The four picture element data y1 to y4 is selected sequentially by theselector 45 and is supplied to a scanning conversion circuit 48. Thescanning conversion circuit 48 generates picture element data of the HDpicture in the order of raster scanning at an output terminal 49. Amonitor for HD is connected to the output terminal 49 through a D/Aconverter (not shown). The number of picture elements of an outputpicture is four times that of picture elements of an input SD videosignal.

FIG. 7 shows one example of a structure for generating the mappingtables M1 to M4 stored in the memories 44a to 44d. In FIG. 7, a digitalHD video signal is supplied to an input terminal indicated at 51. It isdesirable that the HD video signal is a standard-like signal taking intoaccount the generation of the mapping tables. Actually, by taking astandard picture with a HD video camera or by recording a taken picturesignal onto HDVTR, a HD video signal can be provided.

The HD video signal is supplied to a simultaneous output circuit 52. Thesimultaneous output circuit 52 simultaneously produces picture elementdata a to 1 and y1 to y4 having a relationship in positions shown inFIG. 6. The picture element data a to 1 is supplied to a clusteringcircuit 53. The clustering circuit 53 performs the classification ofgradation, patterns, etc., as in the above-mentioned one embodiment. Theoutput of the clustering circuit 53 is commonly given to mapping tablegenerating circuits 54a to 54d.

The picture element data y1 to y4 is supplied to the mapping tablegenerating circuits 54a to 54d which have the same construction. The onesimilar to the structure for obtaining average value as shown in FIG. 4can be adopted for the mapping table generating circuits 54a to 54d. Inthe case of the mapping table generating circuit 54a, y1a is supplied inplace of the picture element data x in FIG. 4. For the mapping tablegenerating circuit 54a, the same structure of FIG. 4 can be employed. Inaddition, with the use of parameters, the same structure as FIG. 3 maybe used for mapping generating circuits 54a to 54d.

Mapping tables showing the correlation between the HD video signal andthe SD video signal are stored in the mapping table generating circuits54a to 54d. In other words, when plural data of the SD video signal isgiven, a mapping table, which outputs picture element data of the HDvideo signal on the average corresponding to the one provided byclustering these a plural data, can be formed. This mapping table isstored in the memories 44a to 44d with the structure of FIG. 5.

Although the above-mentioned one embodiment is an example where theup-conversion of the SD video signal to the HD video signal is made, theinvention can be applied similarly to the enlargement of a picture,besides this embodiment.

According to the invention, data transmitted with a thinning-out systemcan be received, and a thinned picture element can be interpolatedwithout the deterioration of resolution. When picture element datalacking at the time of picture element enlargement is interpolated, theinvention is applicable in a similar manner. Also, the invention notonly permits a video signal with standard resolution to be converted tothat with high resolution but also allows a picture with high resolutionto be displayed on a monitor.

Having described specific preferred embodiments of the present inventionwith reference to the accompanying drawings, it is to be understood thatthe invention is not limited to those precise embodiments, and thatvarious changes and modifications may be effected therein by one skilledin the art without departing from the scope or the spirit of theinvention as defined in the appended claims.

1. Digital data conversion apparatus, comprising: memory means forstoring class data for respective classes at addresses corresponding tosaid respective classes, said class data being associated with referenceinterpolated data and a reference standard definition digital videosignal for each of said respective classes, said reference standarddefinition digital video signal and said reference interpolated dataconstituting a reference high definition digital video signal; means forreceiving a standard definition digital video signal including aplurality of pixel data representing pixel values; means for clusteringsaid pixel data of said standard definition digital video signal toproduce a class in accordance with the pixel values of said pixel data;means for retrieving said class data from the one of said addresses ofsaid memory means corresponding to said class of said standarddefinition digital video signal; and means for generating a plurality ofinterpolated data in accordance with said standard definition digitalvideo signal and said retrieved class data, in which a position of atleast one of said clustered pixel data of said standard definitiondigital video signal is spatially located at the same position of atleast one of said generated interpolated data.
 2. The digital dataconversion apparatus as claimed in claim 1, wherein said class dataincludes a plurality of coefficient data; and wherein said means forgenerating said plurality of interpolated data generates each of saidinterpolated data by adding respective products of a respective one ofsaid coefficient data and a respective one of said pixel data.
 3. Thedigital data conversion apparatus as claimed in claim 1, wherein thestandard definition digital video signal is an orthogonally converteddigital video signal and said means for receiving comprises means fordecoding said orthogonally converted digital video signal to produce adecoded digital video signal.
 4. The digital data conversion apparatusas claimed in claim 1, wherein said class data stored in said memorymeans corresponds to said interpolated data; and wherein said means forgenerating is operable to generate said interpolated data by providingsaid retrieved class data as said interpolated data.
 5. A digital dataconversion method, comprising the steps of: storing class data forrespective classes at addresses in a memory corresponding to saidrespective classes, said class data being associated with referenceinterpolated data and a reference standard definition digital videosignal for each of said respective classes, said reference standarddefinition digital video signal and said reference interpolated dataconstituting a reference high definition digital video signal; receivinga standard definition digital video signal including a plurality ofpixel data representing pixel values; clustering said pixel data of saidstandard definition digital video signal to produce a class inaccordance with the pixel values of said pixel data; retrieving saidclass data from the one of said addresses in said memory correspondingto said class of said standard definition digital video signal; andgenerating a plurality of interpolated data in accordance with saidstandard definition digital video signal and said retrieved class data,in which a position of at least one of said clustered pixel data of saidstandard definition digital video signal is spatially located at thesame position of at least one of said generated interpolated data. 6.The digital data conversion method as claimed in claim 5, wherein saidclass data includes a plurality of coefficient data; and wherein thestep of generating said plurality of interpolated data is carried out byadding respective products of a respective one of said coefficient dataand a respective one of said pixel data.
 7. The digital data conversionmethod as claimed in claim 5, wherein the standard definition digitalvideo signal is an orthogonally converted digital video signal and thestep of receiving further comprises decoding said orthogonally converteddigital video signal to produce a decoded digital video signal.
 8. Thedigital data conversion method as claimed in claim 5, wherein said classdata stored in said memory corresponds to said interpolated data; andwherein said step of generating said interpolated data is carried out byproviding said retrieved class data as said interpolated data. 9.Digital data conversion apparatus for converting a video signaladmitting of a first standard into a video signal admitting of a secondstandard, a resolution of said video signal admitting of said firststandard being lower than a resolution of said video signal admitting ofsaid second standard, comprising: memory means for storing class datafor respective classes at addresses corresponding to said respectiveclasses, said class data being associated with reference output data andreference input data admitting of said first standard for each of saidrespective classes, said reference input data admitting of said firststandard and said reference output data constituting a reference digitalvideo signal admitting of said second standard; means for receiving aninput digital video signal including a plurality of pixel data andadmitting of said first standard; means for clustering said pixel dataof said input digital video signal to produce a class in accordance withvalues of said pixel data; means for retrieving said class data from oneof said addresses of said memory means corresponding to said class ofsaid input digital video signal admitting of said first standard; andmeans for generating a plurality of interpolated data in accordance withsaid input digital video signal and said class data which has beenretrieved, said interpolated data and said input digital video signalconstituting a signal admitting of said second standard, and wherein aposition of at least one of said clustered pixel data of said inputdigital video signal is spatially located at the same position of atleast one of said generated interpolated data.
 10. The digital dataconversion apparatus as claimed in claim 9, wherein said class dataincludes a plurality of coefficient data; and wherein said means forgenerating said plurality of interpolated data is operable to generateeach of said interpolated data by adding respective products of arespective one of said coefficient data and a respective one of saidpixel data.
 11. The digital data conversion apparatus as claimed inclaim 9, wherein said class data stored in said memory means correspondsto said interpolated data; and wherein said means for generating isoperable to generate said interpolated data by providing said retrievedclass data as said interpolated data.
 12. The digital data conversionapparatus as claimed in claim 9, further comprising means for generatingsaid class data stored in said memory means.
 13. Digital data conversionapparatus, comprising: means for generating class data associated withreference interpolated data and reference standard definition digitalvideo signal for each of a plurality of respective classes, saidreference standard definition digital video signal and said referenceinterpolated data constituting a reference high definition digital videosignal; memory means for storing said class data for said respectiveclasses of addresses corresponding to said respective classes; means forreceiving a standard definition digital video signal having a pluralityof pixel data; means for clustering said pixel data of said standarddefinition digital video signal to produce a class in accordance withvalues of said pixel data; means for retrieving said class data from theone of said addresses of said memory means corresponding to said classof said standard definition digital video signal; and means forgenerating a plurality of interpolated data in accordance with saidstandard definition digital video signal and said retrieved class data,in which a position of at least one of said clustered pixel data of saidstandard definition digital video signal is spatially located at thesame position of at least one of said generated interpolated data.
 14. Adigital data conversion method, comprising the steps of: generatingclass data associated with reference interpolated data and a referencestandard definition digital video signal for each of a plurality ofrespective classes, said reference standard definition digital videosignal and said reference interpolated data constituting a referencehigh definition digital video signal; storing said class data for saidrespective classes at addresses in a memory corresponding to saidrespective classes; receiving a standard definition digital video signalhaving a plurality of pixel data; clustering said pixel data of saidstandard definition digital video signal to produce a class inaccordance with values of said pixel data; retrieving said stored classdata from the one of said addresses corresponding to said class of saidstandard definition digital video signal; and generating a plurality ofinterpolated data in accordance with said standard definition digitalvideo signal and said retrieved class data, in which a position of atleast one of said clustered pixel data of said standard definitiondigital video signal is spatially located at the same position of atleast one of said generated interpolated data.
 15. A digital signalconversion apparatus for converting a first digital image signal to asecond digital image signal having a high resolution component,comprising: a memory for storing class data for respective classes ataddresses corresponding to said respective classes, said class dataobtained on the basis of at least a digital image signal having saidhigh resolution component; means for receiving said first digital imagesignal including pixel data representing pixel values; means forclustering a plurality of pixel data of said first digital image signaladjacent to a pixel data of said second digital image signal to producea class, a bit number of said pixel data of said first digital imagesignal being reduced; means for retrieving said class data from one ofsaid addresses of said memory corresponding to said class of said firstdigital image signal; and means for generating all of pixel data,representing pixel values of said second digital image signal, in thesame manner in accordance with a common algorithm based upon at leastsaid retrieved class data in which a position of at least one of saidclustered pixel data is spatially located at the same position of atleast one of said generated data.
 16. The digital signal conversionapparatus as claimed in claim 15, wherein said class data includes aplurality of coefficient data; and wherein said means for generatingsaid pixel data representing pixel values of said second digital imagesignal generates each of said pixel data representing pixel values ofsaid second digital image signal in accordance with the plurality ofcoefficient data and a plurality of pixel data of said first digitalimage signal.
 17. The digital signal conversion apparatus as claimed inclaim 15, wherein the first digital image signal is an orthogonallyconverted digital image signal and said means for receiving comprisesmeans for decoding said orthogonally converted digital image signal toproduce a decoded digital image signal.
 18. The digital signal dataconversion apparatus as claimed in claim 15, wherein said class datastored in said memory corresponds to said pixel data representing pixelvalues of said second digital image signal; and wherein said means forgenerating is operable to generate said pixel data representing pixelvalues of said second digital image signal by providing said retrievedclass data as said pixel data representing pixel values of said seconddigital video signal.
 19. A digital signal data conversion method forconverting a first digital image signal to a second digital image signalhaving a high resolution component, comprising the steps of: storingclass data for respective classes at addresses in a memory correspondingto said respective classes, said class data obtained on the basis of atleast a digital image signal having said high resolution component;receiving said first digital image signal including pixel datarepresenting pixel values; clustering a plurality of pixel data of saidfirst digital image signal adjacent to a pixel data of said seconddigital image signal to produce a class, a bit number of said pixel dataof said first digital image signal being reduced; retrieving said classdata from one of said addresses of said memory corresponding to saidclass of said first digital video signal; and generating all of pixeldata, representing pixel values of said second digital image signal, inthe same manner in accordance with a common algorithm based upon atleast said retrieved class data in which a position of at least one ofsaid clustered pixel data is spatially located at the same position ofat least one of said generated data.
 20. The digital signal conversionmethod as claimed in claim 19, wherein said class data includes aplurality of coefficient data; and wherein the step of generating saidpixel data representing pixel values of said second digital video signalgenerates each of said pixel data representing pixel values of saidsecond digital image signal in accordance with the plurality ofcoefficient data and a plurality of pixel data of said first digitalimage data.
 21. The digital signal conversion method as claimed in claim19, wherein the first digital image signal is an orthogonally converteddigital image signal and the step of receiving further comprisesdecoding said orthogonally converted digital image signal to produce adecoded digital image signal.
 22. The digital signal conversion methodas claimed in claim 19, wherein said class data stored in said memorycorresponds to said pixel data representing pixel values of said seconddigital image signal and wherein said step of generating said pixel datarepresenting pixel values of said second digital image signal is carriedout by providing said retrieved class data as said pixel datarepresenting pixel values of said second digital image signal.
 23. Adigital signal conversion apparatus for converting a digital videosignal admitting of a first standard into a digital video signaladmitting of a second standard, a first resolution of said digital videosignal admitting of said first standard being lower than a secondresolution of said digital video signal admitting of said secondstandard, comprising: a memory for storing class data for respectiveclasses at addresses corresponding to said respective classes, saidclass data obtained on the basis of at least a digital video signaladmitting of said second standard having said second resolution; meansfor receiving an input digital video signal including pixel data andadmitting of said first standard; means for clustering a plurality ofpixel data of said input digital video signal adjacent to a pixel dataof a digital video signal admitting of said second standard to produce aclass, a bit number of said pixel data of said input digital videosignal being reduced; means for retrieving said class data from one ofsaid addresses of said memory corresponding to said class of said inputdigital video signal admitting of said first standard; means forgenerating all of pixel data, representing pixel values of said digitalvideo signal admitting of said second standard, in the same manner inaccordance with a common algorithm based upon at least said class datawhich has been retrieved in which a position of at least one of saidclustered pixel data of said digital video signal admitting of saidfirst standard is spatially located at the same position of at least oneof said generated data.
 24. The digital signal conversion apparatus asclaimed in claim 23, wherein said class data includes a plurality ofcoefficient data; and wherein said means for generating said pixel datarepresenting pixel values of said digital video signal admitting of saidsecond standard is operable to generate each said pixel datarepresenting pixel values of said digital video signal admitting of saidsecond standard in accordance with the plurality of coefficient data anda plurality of pixel data of said digital video signal admitting of saidfirst standard.
 25. The digital signal conversion apparatus as claimedin claim 23, wherein said class data stored in said memory correspondsto said pixel data representing pixel values of said digital videosignal admitting of said second standard and wherein said means forgenerating is operable to generate said pixel data representing pixelvalues of said digital video signal admitting of said second standard byproviding said retrieved class data as said pixel data representingpixel values of said digital video signal admitting of said secondstandard.
 26. The digital signal conversion apparatus as claimed inclaim 23, further comprising means for generating said class data storedin said memory.
 27. A digital signal conversion apparatus for convertinga standard definition digital video signal to a high definition digitalvideo signal, comprising: a memory for storing class data for respectiveclasses at addresses corresponding to said respective classes, saidclass data obtained on the basis of at least a digital video signalhaving a high resolution component; means for receiving said standarddefinition digital video signal having pixel data representing pixelvalues; means for clustering a plurality of pixel data of said standarddefinition digital video signal adjacent to a pixel data of said highdefinition digital video signal to produce a class, a bit number of saidpixel data of said standard definition digital video signal beingreduced; means for retrieving said class data from one of said addressesof said memory corresponding to said class of said standard definitiondigital video signal; and means for generating all of pixel data,representing pixel values of said high definition digital video signal,in the same manner in accordance with a common algorithm based upon atleast said retrieved class data in which a position of at least one ofsaid clustered pixel data of said standard definition digital videosignal is spatially located at the same position of at least one of saidgenerated data.
 28. The digital signal conversion apparatus as claimedin claim 27, wherein said class data includes a plurality of coefficientdata; and wherein said means for generating the pixel data representingpixel values of said high definition digital video signal generates eachof said pixel data representing values of said high definition digitalvideo signal in accordance with the plurality of coefficient data and aplurality of pixel data of said standard definition digital videosignal.
 29. The digital signal conversion apparatus as claimed in claim28, wherein said class data stored in said memory corresponds to saidpixel data representing pixel values of said high definition digitalvideo signal; and said means for generating is operable to generate saidpixel data representing pixel values of said high definition digitalvideo signal by providing said retrieved class data as said pixel datarepresenting pixel values of said high definition digital video signal.30. A digital signal conversion method, comprising the steps of: storingclass data for respective classes at addresses in a memory correspondingto said respective classes, said class data obtained on the basis of atleast a digital video signal having a high resolution component;receiving a standard definition digital video signal having pixel datarepresenting pixel values; clustering a plurality of pixel data of saidstandard definition digital video signal adjacent to a pixel data of ahigh definition digital video signal to produce a class, a bit number ofsaid pixel data of said standard definition digital video signal beingreduced; retrieving said stored class data from one of said addressescorresponding to said class of said standard definition digital videosignal; and generating all of pixel data, representing pixel values ofsaid high definition digital video signal, in the same manner inaccordance with a common algorithm based upon at least said retrievedclass data in which a position of at least one of said clustered pixeldata of said standard definition digital video signal is spatiallylocated at the same position of at least one of said generated data. 31.The digital signal conversion method as claimed in claim 30, whereinsaid class data includes a plurality of coefficient data; and whereinsaid step for generating the pixel data representing pixel values ofsaid second output digital video signal generates each of said pixeldata representing values of a high definition video signal in accordancewith the plurality of coefficient data and a plurality of pixel data ofsaid standard definition digital video signal.
 32. The digital signalconversion method as claimed in claim 30, wherein said stored class datacorresponds to said pixel data representing pixel values of said secondoutput digital video signal; and said step for generating is operable togenerate said pixel data representing pixel values of said second outputdigital video signal by providing said retrieved class data as pixeldata representing pixel values of a high definition digital videosignal.
 33. A digital data conversion apparatus for converting a firstdigital image signal to a second digital image signal having a highresolution component, comprising: a memory for storing class data forrespective classes at addresses corresponding to said respectiveclasses, said class data obtained on the basis of at least digital imagedata having said high resolution component; means for receiving saidfirst digital image signal including pixel data representing pixelvalues; means for clustering a plurality of pixel data of said firstdigital image signal adjacent to a plurality of pixel data of saidsecond digital image signal to produce a class, a bit number of saidpixel data of said first digital image signal being reduced and saidclass being used to retrieve a class data to generate a plurality ofpixel data representing pixel values of said second digital imagesignal; means for retrieving said class data from addresses of saidmemory corresponding to said class of said first digital image signal;and means for generating all of said pixel data, representing pixelvalues of said second digital image signal, in the same manner inaccordance with a common algorithm based upon at least said retrievedclass data in which a position of at least one of said clustered pixeldata is spatially located at the same position of at least one of saidgenerated data.
 34. The digital data conversion apparatus as claimed inclaim 33, wherein said class data includes a plurality of coefficientdata; and wherein said means for generating the plurality of pixel datarepresenting pixel values of said second digital image signal generateseach of said pixel data representing values of said second digital imagesignal in accordance with the plurality of coefficient data and aplurality of pixel data representing pixel values of said first digitalimage data.
 35. The digital data conversion apparatus as claimed inclaim 33, wherein said class data stored in said memory corresponds tosaid pixel data representing pixel values of said second digital imagesignal; and said means for generating is operable to generate said pixeldata representing pixel values of said second digital image signal byproviding said retrieved class data as said pixel data representingpixel values of said second digital image signal.
 36. A digital dataconversion method for converting a first digital image signal to asecond digital image signal having a high resolution component,comprising the steps of: storing class data for respective classes ataddresses in a memory corresponding to said respective classes, saidclass data obtained on the basis of at least digital image data havingsaid high resolution component; receiving said first digital imagesignal including pixel data representing pixel values; clustering aplurality of pixel data of said first digital image signal adjacent to aplurality of pixel data of said second digital image signal to produce aclass, a bit number of said pixel data of said first digital imagesignal being reduced and said class being used to retrieve a class datato generate a plurality of pixel data representing pixel values of saidsecond digital image signal; retrieving said class data from addressesof said memory corresponding to said class of said first digital imagesignal; and generating all of said pixel data, representing pixel valuesof said second digital image signal, in the same manner in accordancewith a common algorithm based upon said retrieved class data in which aposition of at least one of said clustered pixel data is spatiallylocated at the same position of at least one of said generated data. 37.The digital data conversion method as claimed in claim 36, wherein saidclass data includes a plurality of coefficient data; and wherein saidstep for generating the plurality of pixel data representing pixelvalues of said second digital image signal generates each of said pixeldata representing values of said second digital image signal inaccordance with the plurality of coefficient data and a plurality ofpixel data representing pixel values of said first digital image data.38. The digital data conversion method as claimed in claim 36, whereinsaid class data stored in said memory corresponds to said pixel datarepresenting pixel values of said second digital image signal; and saidstep for generating is operable to generate said pixel data representingpixel values of said second digital image signal by providing saidretrieved class data as said pixel data representing pixel values ofsaid second digital image signal.